Method for forming copper-containing metal studs

ABSTRACT

The method of the present invention is related to the fabrication of a copper-based multilevel interconnect structure. This copper-based multilevel interconnect structure is based on the formation of vertical metal connections through copper-containing metal stud growth on an underlying horizontal metal pattern, followed by a stud encapsulation step against copper diffusion into the surrounding dielectric, i.e. the insulating layers. This method is of particular interest when the insulating layers used to obtain this interconnect structure are polymer layers with a low dielectric constant and preferably with a high degree of planarization.

FIELD OF THE INVENTION

[0001] The present invention is related to the formation of verticalconductive connections, particularly metal studs. Such connections canbe implemented in metallization structures used for interconnectingintegrated circuits.

BACKGROUND OF THE INVENTION

[0002] The ongoing focus on miniaturisation and the increasingcomplexity and speed requirements of integrated circuits demand for acontinuous higher density integration. To achieve this, there is anongoing downscaling in the dimensions of the active devices as well asof the structures interconnecting these devices. These interconnectstructures can comprise multiple metal levels which are, dependent onthe aimed interconnect pattern, either separated one from another bymeans of interlevel insulating layers or connected one to the other bymeans of a conductive connection through the insulating layer. Besidesthis downscaling of the dimensions, additional measures are required tobe able to meet the stringent speed specifications, i.e. the signaldelay. Conventionally the metal levels are Aluminum layers while theinsulating layers are oxide layers. Therefore, in order to reduce thesignal delay one can choose a metal layer with a higher conductivitycompared to Aluminum and/or choose insulating layers with a lowerdielectric constant compared to oxide layers. To meet these objectivesCu-containing metal layers and/or Cu-containing connections are or willbe introduced in the near future.

[0003] The use of Cu in interconnect structures also has some commonlyknown disadvantages. At first, Cu can have a high diffusion in thesurrounding insulating layers which negatively affects the reliabilityand the signal delay. Secondly, Cu easily oxidizes, especially at highertemperatures. Further, it is difficult to pattern Cu by means ofreactive ion etching (RIE) because, amongst others, a high temperatureis required and volatile Cu-compounds have to be found to etch copper.

[0004] Nowadays, there a two major ways of fabricating interconnectstructures. In the conventional way as a start a conductive layer, i.e.a metal layer, is formed on an insulating layer (or on the substrate)and patterned thereafter usually by means of RIE. When a damascenetechnology is used, first an insulating layer is deposited and patternedand thereafter the conductive layer is deposited to fill the openings,eventually followed by a planarization step to remove the metal excess.Both ways still require adequate barrier layers to prevent the diffusionof Cu in the insulating layer. The damascene technology has theadvantage that the difficult Cu RIE step is avoided. Damasceneprocessing reduces the problem to dry etching of an insulating layer ora stack of insulating layers. The final planarization step yields inlaidhorizontal copper interconnect lines in a planar topology. The addedbonus of damascene processing is a substantial decrease in the costfactor compared to classical aluminum RIE processing. An expected costreduction of about 30% has been calculated. The use of plating methodssuch as electroless and electrolytic copper plating is anticipated tofurther decrease the cost.

[0005] As stated before, due to the difficulty of RIE etching of copperlayers, the major processing route for fabricating interconnectstructures will be damascene processing, particularly dual damasceneprocessing. This technique allows to build up horizontal metal patternsas well as vertical metal connections in the surrounding insulatinglayers. These vertical metal connections are required in order to beable to provide a conductive connection between two horizontal metalpatterns being processed in different metal levels. To provide such aconnection, usually first openings have to be formed in the insulatinglayer or in the stack of insulating layers between two different metallevels and filled thereafter with a conductive material. Examples ofsuch openings are via holes or contact holes or trenches. To meet thehigh density integration requirements, the diameter of these openings iscontinuously decreasing, while at the same time the aspect ratio ofthese openings is increasing. Due to the small diameter and the highaspect ratios, the creation of these opening, especially thelithographic steps and the dry etchings steps involved, as well as theconformal filling of these openings with a metal or the combination of ametal and a barrier layer poses severe problems.

[0006] In patent application U.S. Pat. No. 4,873,565, incorporatedherein by reference, an interconnection between metallization layers ofa semiconductor device separated by an insulator is disclosed. A lead iscovered with a diffusion barrier layer and a stud is formed above thediffusion barrier layer. Afterwards, the stud is covered with acorrosion preventing material on the sidewalls and on the top surface ofthe stud. The insulating material is then applied over the conductor anda second metallization level covers the insulating layer. Using thiskind of interconnects, problems related to reliability and waste spaceof the surface area are eliminated. The above mentioned method does nottake in account the problem of out-diffusion of copper in thesurrounding insulating layer.

[0007] In patent application U.S. Pat. No. 4,866,008, incorporatedherein by reference, the authors provide a method of forming aself-aligned conductive pillar on a lower level metallizationinterconnect to an upper level metallization. This invention focuses onthe method by which the conductive pillars are formed by a self-alignedprocess over the first metallization interconnect with advantages inincreased packaging density of structures on the device and a reducedcurrent density in the conductive pillars.

AIM OF THE INVENTION

[0008] It is an aim of the invention to provide a solution to theproblem of making vertical Cu-containing metal connections between twohorizontal metal patterns being formed in two different metal levels andto provide a solution to the problem of diffusion of copper from themetal connection in the surrounding insulating layers. The method of thepresent invention avoids the inherent dry etching problem for theformation of openings in the interlevel insulating layer stack,especially for openings with a small diameter and a high aspect ratio,both for the conventional way of making interconnect structures as wellas for a damascene technology. The method also circumvents the inherentdry etching problem for the formation of openings in the interlevelinsulating layer stack, especially for openings with a small diameterand a high aspect ratio, both for the conventional way of makinginterconnect structures as well as for a damascene technology.

[0009] It is a further aim of the invention to fabricate Cu-containingmetal studs.

SUMMARY OF THE INVENTION

[0010] The method of the present invention is related to a copper-basedmultilevel interconnect structure. This copper-based multilevelinterconnect structure is based on the formation of vertical metalconnections through copper stud growth on an underlying horizontal metalpattern, followed by an optional copper stud encapsulation step againstcopper diffusion into the surrounding dielectric, i.e. the insulatinglayers. Therefore, in an aspect of the invention a method for formingCu-containing metal studs is disclosed comprising the steps of:

[0011] a) depositing a resist layer on a conductive pattern;

[0012] b) patterning said resist layer by a sequence of at least alithographic and a removal step to thereby form an opening in saidresist layer, said opening extending down to the surface of saidconductive pattern;

[0013] c) depositing a Cu-containing metal to fill up said opening; and

[0014] d) removing said resist layer to thereby free the Cu-containingmetal stud formed on said conductive layer.

[0015] The method of the invention can further comprise the steps of:

[0016] e) encapsulating said Cu-containing metal stud. Thisencapsulation can be performed in order to prevent out-diffusion of Cuin the surrounding insulating layers. Alternatively, particularly theresist layer, deposited in step a), can be a permanent polymer layerinstead of a sacrificial resist layer. Preferably this permanent polymerlayer has a low dielectric constant. In this case, the removal step,i.e. step d) is omitted.

[0017] In another embodiment of the invention, after coverage of thecopper studs preferably with a planarizing polymer with a low dielectricconstant, trench etching is performed in a single damascene process stepwhich opens up the underlying copper via studs. Therefore, a method offorming an interconnect structure is disclosed, wherein after aCu-containing metal stud is formed, said method further comprises thesteps of:

[0018] f) depositing an insulating layer, said insulating layer coveringsaid stud;

[0019] g) forming a patterned hard mask layer on said insulating layer;and

[0020] h) etching said insulating layer using said patterned hard masklayer as a mask to form an opening at least down to the surface of saidCu-containing metal stud.

[0021] In another embodiment of the invention, a method to obtain a dualdamascene interconnect structure is disclosed without the inherentproblem of dry etching of openings, i.e. contact openings, via openingsand trenches. This method is for instance of interest when theinsulating layers used to obtain this interconnect structure are polymerlayers with a low dielectric constant and preferably with a high degreeof planarization. A method for forming an interconnect structure isdisclosed comprising the steps of:

[0022] a) depositing a resist layer on a conductive pattern;

[0023] b) patterning said resist layer by a sequence of at least alithographic and a removal step to thereby form an opening in saidresist layer, said opening extending down to the surface of saidconductive pattern;

[0024] c) depositing a Cu-containing metal to fill up said opening;

[0025] d) removing said resist layer to thereby free the Cu-containingmetal stud formed on said conductive layer;

[0026] e) encapsulating said Cu-containing metal stud;

[0027] f) depositing an insulating layer, said insulating layer coveringsaid stud;

[0028] g) forming a patterned hard mask layer on said insulating layer;and

[0029] h) etching said insulating layer using said patterned hard masklayer as a mask to form an opening at least down to the surface of saidencapsulated Cu-containing metal stud.

BRIEF DESCRIPTION OF THE DRAWINGS

[0030]FIG. 1 depicts, according to an embodiment of the invention, aschematic process flow used to create a dual-damascene structure(right-hand side of the drawings) as well as a classical metal structure(left-hand side of the drawings) both based on the formation ofCu-containing metal studs.

DETAILED DESCRIPTION OF THE INVENTION

[0031] In relation to the appended drawings the present invention isdescribed in detail in the sequel. It is apparent however that a personskilled in the art can imagine several other equivalent embodiments orother ways of executing the present invention, the spirit and scope ofthe present invention being limited only by the terms of the appendedclaims.

[0032] The method of the present invention allows the fabrication of acopper-based multilevel interconnect structure. This copper-basedmultilevel interconnect structure is based on the formation of verticalmetal connections through copper stud growth on an underlying horizontalmetal pattern, followed by a copper stud encapsulation step againstcopper diffusion into the surrounding dielectric, i.e. in the insulatinglayers. This encapsulation step is preferably a self-aligned step. Inorder to form the Cu studs, first a resist layer is deposited on theunderlying horizontal pattern. Preferably this resist layer is asacrificial polymer layer with a thickness typically in the range from0.2 μm to 3 μm. However, also a permanent polymer layer can be usedpreferably with a low dielectric constant and a high degree ofplanarization. The horizontal metal pattern can comprise at least oneelement selected from the group comprising Cu, a Cu-alloy, Al, anAl-alloy, Ti, Co, Ni, Pt, Ta, TiN, TaN or a compound of one of theprevious elements. Particularly, this horizontal metal pattern can be astack of multiple layers wherein each of the layers is formed withelements of the aforementioned group in order to form the combination ofe.g. a metal layer and a (diffusion) barrier layer, like e.g. Al andTiN, or a metal layer and a contact layer like e.g. Al and TiSi₂, or ametal layer and a conductive (diffusion) barrier layer, like e.g. Cu andTa, or Cu and Co. The horizontal metal pattern can be an inlaidstructure, i.e. being formed in an insulating layer by means of adamascene technology, or a conventional metal pattern being formed on aninsulating layer.

[0033] After the deposition of the resist layer, this layer can bepatterned by a sequence of at least a lithographic and a removal step tothereby form an opening in said resist layer, said opening extendingdown to the surface of said horizontal metal pattern. A Cu-containingmetal is deposited to fill up this opening. In case the polymer layer isa sacrificial one, then this layer is removed e.g. by a wet etchprocess. Finally the Cu can be encapsulated in order to avoid theout-diffusion of the Cu.

[0034] According to an embodiment of the invention, the next processsteps involve embedding of the copper studs in an insulating layer or ina stack of insulating layers for trench formation. Particularly, theinsulating layers which are deposited on the Cu studs, beingencapsulated or not, can be self-planarizing organic polymeric spin-onfilms with a low dielectric constant, i.e. with a dielectric constantsmaller than the dielectric constant of silicon dioxide. The trenchstructures are obtained in a singlestep damascene process by classicalphoto-lithographic patterning of the polymer and trench etch by RIE downto the surface of the underlying encapsulated copper studs using apatterned hard mask layer as a mask. Examples of such hard mask layersare silicon layers selected from the group of oxides, nitrides andoxynitrides. Also a fluorinated silicon oxide can be used. Next, aninlaid metal pattern can be formed by deposition of at least one elementselected from the group comprising Cu, a Cu-alloy, Al, an Al-alloy, Ti,Co, Ni, Pt, Ta, TiN, TaN. Particularly, this metal pattern can be astack of multiple layers wherein each of the layers is deposited withelements selected from the aforementioned group in order to form a stackof e.g. a conductive (diffusion) barrier layer and a metal layer, likee.g. Ta and Cu, or Co and Cu. This inlaid metal pattern contacts the topsurface of the Cu stud. If the Cu-stud is encapsulated in anon-conductive barrier layer, then before the deposition an opening hasto be formed in said barrier layer in order to contact the Cu. Finally,metal and barrier chemical mechanical polishing (CMP) assures that theinlaid metal pattern flushes with the top surface of the dielectric.

[0035] In a preferred embodiment of the invention, an example (FIG. 1)is disclosed to form a dual damascene interconnect structure. The methodcomprises the steps of:

[0036] a) depositing (FIG. 1a)) a resist layer (3) on a conductivepattern (2). According to this example, the resist layer is aphoto-definable sacrificial polymer. Although for the stud formation asacrificial polymer is preferable, a permanent polymer can also be used.The thickness of the photo-polymer typically ranges between about 0.2 μmand 3 μm. The sacrificial or permanent polymer can be applied bysputtering, spin-coating, vapour deposition or epitaxy. The conductivepattern is a horizontal metal pattern comprising at least one elementselected from the group comprising Cu, a Cu-alloy, Al, an Al-alloy, Ti,Co, Ni, Pt, Ta, TiN, TaN or a silicide of one of the previous elements.Particularly, this horizontal metal pattern can be a stack of multiplelayers wherein each of the layers is formed with elements of theaforementioned group. The horizontal metal pattern can be an inlaidstructure, i.e. being formed in an insulating layer (1) by means of adamascene technology, or a conventional metal pattern being formed on aninsulating layer. Both possible structures are shown combined in thedrawings. According to the present invention, it does not matter whichof the two metal pattern technologies is used. They will be discussedtogether in the same drawings. According to this example, a horizontalaluminum pattern is formed in an insulating layer using a damascenetechnology. Preferably the insulating layer is a layer with a lowdielectric constant, i.e. a dielectric constant below 3.9. Particularlythe insulating layer can be an organic polymer layer selected from agroup comprising the benzocyclobutarenes, i.e. benzocyclobutene (BCB)commercially available as Cyclotene 5021™, poly arylene ether, i.e.FLARE™ II, aromatic hydrocarbon, i.e. SILK™, and polyimides. Accordingto this example, the insulating layer is a BCB layer. Amongst others,BCB is selected due to its high degree of planarization and excellentcoverage of an underlying metal pattern.

[0037] According to this embodiment of the invention, the method forforming a dual damascene interconnect structure further comprises thestep of:

[0038] b) patterning said resist layer (FIG. 1b) by a sequence of atleast a lithographic and a removal step to thereby form an opening (4)in said resist layer, said opening extending down to the surface of saidconductive pattern. According to this example, the resist layer is aphoto definable sacrificial polymer, which is exposed and developed tocreate an opening extending down to the surface of the underlyinghorizontal pattern.

[0039] According to this embodiment of the invention, the method forforming a dual damascene interconnect structure further comprises thestep of:

[0040] c) depositing a Cu-containing metal (FIG. 1c)) to fill up saidopening in said resist layer. According to the example, the processproceeds with the formation of metal studs (5) in a sacrificialphoto-definable polymer layer by a deposition. Particularly, a selectivedeposition technology such as e.g. electroless plating can be used.Selective depositing means depositing a material on a predeterminedplace, for instance in an opening. The metal of choice for futuretechnologies is copper. The preferred embodiment of the invention isbased on the creation of openings in a photo-resist layer of adequatethickness, and selective electroless copper deposition into theseopenings onto an underlying horizontal metal pattern. The height of thecopper studs is controlled by the plating time. The electrolessdeposition method is inherently selective, works at low temperatures,and can be performed on many conductive materials such as e.g. TiN,being the ARC layer of a classical aluminumbased metal stack, TaN, beinga diffusion barrier for copper, and also directly on an underlyingcopper layer.

[0041] According to this embodiment of the invention, the method forforming a dual damascene interconnect structure further comprises thestep of:

[0042] d) removing said resist layer (FIG. 1d)) to thereby free the Cumetal stud formed on said conductive layer. After the Cu deposition, theresist layer is removed using a wet etching or a gas chemistry whichdoes not oxidize the copper material. This results in free-standing Cuplugs on top of the underlying horizontal metal pattern.

[0043] According to this preferred embodiment of the invention, themethod for forming a dual damascene interconnect structure furthercomprises the step of:

[0044] e) encapsulating said Cu metal stud. According to the example,after the creation of free-standing copper studs, copper encapsulation(FIG. 1e)) can be performed in order to avoid copper diffusion intoinsulating layer(s) to be deposited in the next process step(s).Particularly, the barrier layer consists of a material selected from agroup consisting of Co, Ta, Ti, TiN, TaN, Si₃N₄, W N and/or compoundsthereof. In W_(x)N, _(x) can vary between 1 and 4 and between 2 and 3.This encapsulation of the copper studs can be done with either aconductive barrier material or with a very thin high qualitynon-conductive copper diffusion barrier such as Si₃N₄, particularly thisSi₃N₄ layer can be deposited by high density Plasma chemical vapourdeposition (CVD). The latter route has the advantage of completeprotection of the underlying devices from vertical copper out-diffusion.However, the formation of openings down to the surface of the Cu stud ina later stage will be more difficult due to the additional etching ofthe Si₃N₄ layer on top of the studs. This additional etching is requiredto ensure an electrical contact. As a consequence, the preferredembodiment is the application of a thin conductive barrier layer (6)which encapsulates the copper studs. The conductive copper barrier layercan be deposited using electroless plating, or a sputtering technique,or by selective or non-selective (blanket) chemical vapour deposition.

[0045] Selective encapsulation has the advantage of being self-alignedand requires only one process step. Particularly, electroless plating,being a selective deposition technique is the preferred technique due toits low cost and the simplicity of processing. Literature relating toselective plating of copper barrier layers such as Co (W, P) is alreadyavailable, as e.g in Y. Shacham-Diamand and S. Y. Lopatin, “High aspectratio quartermicron electroless copper integrated technology”, Materialsfor Advanced Metallization (1997), pp.11-14.

[0046] In an alternative embodiment of the invention instead of aselective deposition technique also a blanket deposition technique canbe used. Blanket deposition of the conductive barrier layer by eitherphysical vapour deposition (PVD) or CVD techniques requiressubstantially more process steps due to the requirement of the barrierlayer patterning. A non-critical lithographic resist pattern identicalto the underlying horizontal metal pattern is formed on the barrierlayer. Then, the barrier layer is patterned by means of a reactive ionetch (RIE) step using the patterned resist layer as a mask. After theRIE step the resist is removed using a wet and/or a dry etching step.

[0047] According to the preferred embodiment of the invention, themethod for forming a dual damascene interconnect structure furthercomprises the steps of:

[0048] depositing (FIG. 1f)) an insulating layer (7), said insulatinglayer covering said stud;

[0049] g) forming (FIG. 1g)) a patterned hard mask layer (8) on saidinsulating layer. Preferably the insulating layer is a layer with a lowdielectric constant. Particularly the insulating layer can be an organicpolymer layer selected from a group comprising the benzocyclobutarenes,i.e. benzocyclobutene (BCB) commercially available as Cyclotene 5021™,poly arylene ether, i.e. FLARE™ II, aromatic hydrocarbon, i.e. SILK™,and polyimides. More particularly, the insulating layer is a layer witha high degree of planarization. According to the example, after theformation of the Cu stud and the optional copper diffusion barrierdeposition, an organic polymer with a low dielectric constant and highintrinsic degree of planarization is deposited. Particularly, a BCBlayer is deposited. The thickness depends on the design rules of thespecific technology wherein these interconnect structures are processed.The deposition is preferably by means of a spin-coating techniquebecause of the high degree of self-planarization on high densitystructures of such a technique. Particularly, this is experimentallyobserved for some of the aforementioned polymeric layers as e.g. BCB. Aplanar insulating layer simplifies the subsequent trench definitionlithography step. Next, a non-conductive hard mask layer is deposited,e.g. using a chemical vapour deposition or a spin-on technique. For thepurpose of this disclosure, a hard mask layer is defined as a layerwhich can be etched selectively to an other layer and which thereforecan be used as an etch mask to etch said other layer. Traditionallithographic resists are not suited to be used as hard mask layers forpatterning organic spin-on materials because these resists are alsobased on organic polymers resulting in an insufficient etch selectivity,particularly in an oxygen-based chemistry, with regard to the organicspin-on material. Therefore inorganic hard mask layers like oxides ornitrides or oxynitrides are used. The non-conductive hard mask layer ispatterned using a fluorine-based RIE chemistry.

[0050] According to the preferred embodiment of the invention, themethod for forming a dual damascene interconnect structure furthercomprises the steps of:

[0051] h) etching (FIG. 1h)) said insulating layer using said patternedhard mask layer as a mask to form an opening (9) at least down to thesurface of said encapsulated Cu metal stud. According to the example,the organic polymer is etched using an oxygen-based RIE chemistry toform an opening, i.e. a trench. The etching of the polymer is timed andhas to be sufficiently long to expose the surface of the encapsulatedcopper stud in order to allow a contact without a high resistance. Inanother embodiment of the invention, if the encapsulation of the Cu studis performed with a non-conductive barrier layer, then also an openinghas to be created through the barrier layer in order to allow alow-ohmic contact to the Cu stud.

[0052] According to an embodiment of the invention, the method forforming a dual damascene interconnect structure further comprises thestep of:

[0053] i) forming an inlaid metal pattern by deposition of at least oneelement selected from the group comprising Cu, a Cu-alloy, Al, anAl-alloy, Ti, Co, Ni, Pt, Ta, TiN, TaN. Particularly, this metal patterncan be a stack of multiple layers wherein each of the layers isdeposited with elements selected from the aforementioned group in orderto form a stack of e.g. a conductive (diffusion) barrier layer an ametal layer, like e.g. Ta and Cu, or Co and Cu. This inlaid metalpattern contacts the top surface of the Cu stud. If the Cu-stud isencapsulated in a non-conductive barrier layer, then before thedeposition an opening has to be formed in said barrier layer in order tocontact the Cu. According to the example (FIG. 1i)) a Ti-basedconductive barrier layer (10) is deposited using PVD, followed by asubsequent deposition of a Cu-containing metal (11). This deposition canbe performed using CVD, or PVD, or electroplating, or electrolessplating. A final chemical mechanical polishing (CMP) step will removethe excess metal and barrier layer. The presence of the remainder ofhard mask layer is beneficial for the CMP step because it serves as aCMP removal stop thereby avoiding the stopping of the CMP step directlyon the underlying polymer. If necessary the remaining hard mask layercan be removed by either a wet etch in dilute HF (no attack of Cu lines)or by a dry etch (after selective capping of the copper lines).

[0054] Finally, an optional barrier layer of e.g. Ti, TiN, Ta, TaN canbe deposited using sputtering (PVD) or CVD and patterned in order toenclose the metal line. In this case, further patterning of the cappinglayer is needed which complicates the process flow. On the other hand,electroless deposition of a barrier metal can be used to selectively capthe copper lines, which simplifies the process flow. In the finalstructure the Cu is then completely encapsulated by a barrier layer in aBCB film.

[0055] An advantage of the preferred embodiment is the absence of anintermittent hard mask layer between the BCB layer which defines the vialevel and the one that defines the trench level. Usually, most classicaldual damascene process flows require the presence of such hard maskinterlayer for etch control The hard mask interlayer has a highdielectric constant, i.e. equal or higher than about 4. Therefore, sucha hard mask layer has a negative effect on the inter-metal levelcapacitance. In the absence of a hard mask layer, the classical dualdamascene processing has to rely on timed etch steps, which could proveto be very difficult to implement in a production environment. Anotheradvantage of the present invention is that barrier layer deposition andcopper filling of the underlying via structures is simplified becausefilling of high aspect ratio trenches and via combinations in a singleprocess step is avoided.

What is claimed is:
 1. A method for forming Cu-containing metal studscomprising the steps of: a) depositing a resist layer on a conductivepattern; b) patterning said resist layer by a sequence of at least onelithographic and at least one removal step to thereby form an opening insaid resist layer, said opening extending down to the surface of saidconductive pattern; c) depositing at least one Cu-containing metal tofill up said opening; and d) removing said resist layer to thereby freethe Cu-containing metal stud formed on said conductive layer e)encapsulating said Cu-containing metal stud by depositing a barrierlayer.
 2. A method as recited in claim 1 wherein said barrier layerconsists of a material selected from a group consisting of Co, Ta, Ti,TiN, TaN, Si₃N ₄, W_(x)N and/or compounds thereof.
 3. A method as inclaim 1, wherein both the Cu-containing metal and the barrier layer areselectively deposited.
 4. A method as in claim 3 wherein both theCu-containing metal and the barrier layer are selectively deposited bymeans of electroless plating
 5. A method for forming an interconnectstructure comprising the steps of: a) depositing a resist layer on aconductive pattern; b) patterning said resist layer by a sequence of atleast one lithographic and at least one removal step to thereby form anopening in said resist layer, said opening extending down to the surfaceof said conductive pattern; c) depositing a Cu-containing metal to fillup said opening; d) removing said resist layer to thereby free theCu-containing metal stud formed on said conductive layer; e)encapsulating said Cu-containing metal stud; f) depositing an insulatinglayer, said insulating layer covering said stud; g) forming a patternedhard mask layer on said insulating layer; and h) etching said insulatinglayer using said patterned hard mask layer as a mask to form an openingat least down to the surface of said encapsulated Cu-containing metalstud.
 6. A method as in claim 5, wherein said Cu-containing metal studis encapsulated by depositing a barrier layer of a material selectedfrom a group comprising Co, Ta, Ti, TiN, TaN, Si₃N₄, W_(x)N and/orcompounds thereof.
 7. A method as in claim 5 wherein the insulatinglayer is a layer with a dielectric constant below 3.9.
 8. A method as inclaim 5, wherein the insulating layer is an organic polymer layer.
 9. Amethod as in claim 8 wherein the organic polymer layer is selected froma group comprising the benzocyclobutarenes, poly arylene ether, aromatichydrocarbon and polyimides.
 10. A method as in claim 5 wherein the hardmask layer is selected from a group comprising silicon oxide, siliconnitrides and silicon oxynitrides.